? semiconductor components industries, llc, 2013 december, 2013 ? rev. 1 1 publication order number: ncp432/d ncp432, ncp433 1.5a ultra-small controlled load switch with auto-discharge path the ncp432 and ncp433 are a low ron mosfet controlled by external logic pin, allowing optimization of battery life, and portable device autonomy. indeed, due to a current consumption optimization with pmos structure, leakage currents are eliminated by isolating connected ic?s on the battery when not used. output discharge path is also embedded to eliminate residual voltages on the output (ncp433 only). proposed in wide input voltage range from 1.0 v to 3.6 v, and a very small 0.76 x 0.76 mm wlcsp4, 0.4 mm pitch. features ? 1 v ? 3.6 v operating range ? 50 m p mosfet at 1.8 v ? dc current up to 1.5 a ? output auto ? discharge (ncp433) ? active high en pin ? wlcsp4 0.76 x 0.76 mm ? these devices are pb ? free, halogen free/bfr free and are rohs compliant typical applications ? mobile phones ? tablets ? digital cameras ? gps ? portable devices en enx dcdc converter 0 platform ic?n v+ ls or ldo ncp433 out a1 gnd b1 in a2 en b2 figure 1. typical application circuit http://onsemi.com see detailed ordering and shipping information on page 6 of this data sheet. ordering and marking information wlcsp4 case 567fj marking diagram xx xx = av or at pinout (top view) out in en gnd 12 a b
ncp432, ncp433 http://onsemi.com 2 pin function description pin name pin number type description in a2 power load ? switch input voltage; connect a 1 f or greater ceramic capacitor from in to gnd as close as possible to the ic. gnd b1 power ground connection. en b2 input enable input, logic high turns on power switch. out a1 output load ? switch output; connect a 1 f ceramic capacitor from out to gnd as close as possible to the ic is recommended. block diagram figure 2. block diagram
ncp432, ncp433 http://onsemi.com 3 maximum ratings rating symbol value unit in, out, en, pins: v en, v in, v out ? 0.3 to + 4.0 v from in to out pins: input/output v in, v out 0 to + 4.0 v maximum junction temperature t j ? 40 to + 125 c storage temperature range t stg ? 40 to + 150 c human body model (hbm) esd rating are (notes 1 and 2) esd hbm 7000 v machine model (mm) esd rating are (notes 1 and 2) esd mm 250 v charge device model (cdm) esd rating are (notes 1 and 2) esd cdm 2000 v latch ? up protection (note 3) ? pins in, out, en lu 100 ma moisture sensitivity (note 4) msl level 1 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. according to jedec standard jesd22 ? a108. 2. this device series contains esd protection and passes the following tests: human body model (hbm) 7.0 kv per jedec standard: jesd22 ? a114 for all pins. machine model (mm) 250 v per jedec standard: jesd22 ? a115 for all pins. charge device model (cdm) 2.0 kv per jedec standard: jesd22 ? c101 for all pins. 3. latch up current maximum rating: 100 ma per jedec standard: jesd78 class ii. 4. moisture sensitivity level (msl): 1 per ipc/jedec standard: j ? std ? 020. operating conditions symbol parameter conditions min typ max unit v in operational power supply 1.0 3.6 v v en enable voltage 0 3.6 t a ambient temperature range ? 40 25 +85 c c in decoupling input capacitor 1 f c out decoupling output capacitor 1 f r ja thermal resistance junction to air wlcsp package (note 5) 150 c/w i out maximum dc current 1.5 a p d power dissipation rating (note 6) t a 25 c wlcsp package 0.5 w t a = 85 c wlcsp package 0.2 w 5. the r ja is dependent of the pcb heat dissipation and thermal via. 6. the maximum power dissipation (p d ) is given by the following formula:
ncp432, ncp433 http://onsemi.com 4 electrical characteristics min & max limits apply for t a between ? 40 c to +85 c for v in between 1.0 v to 3.6 v (unless otherwise noted). typical values are referenced to t a = + 25 c and v in = 3.3 v (unless otherwise noted). symbol parameter conditions min typ max unit power switch r ds(on) static drain ? source on ? state resistance v in = 3.6 v t a = 25 c, i = 200 ma (note 8) 35 m t a = 85 c 55 v in = 3.3 v t a = 25 c, i = 200 ma 37 t a = 85 c 60 v in = 1.8 v t a = 25 c, i = 200 ma 50 t a = 85 c 80 v in = 1.2 v t a = 25 c, i = 200 ma 100 t a = 85 c 150 v in = 1.1 v t a = 25 c, i = 100 ma 120 r dis output discharge path en = low v in = 3.3 v, ncp433 only 40 65 90 t r output rise time v in = 3.6 v c load = 1 f, r load = 25 (note 7) from 10% to 90% of v out 5 20 40 s t f output fall time c load = 1 f, r load = 25 (note 7) 20 56 80 s t on gate turn on gate turn on + output rise time 20 47 115 s t en enable time from en low to high to v out 10% 15 30 75 s t dis disable time from en high to low to v out = 90% of fully on 2 11 20 s v ih high ? level input voltage 0.9 v v il low ? level input voltage 0.5 v quiescent current i q current consumption v in = 3.3 v, en = low, no load 0. 01 0.6 a v in = 3.3 v, en = high, no load 0. 2 0.6 a 7. parameters are guaranteed for c load and r load connected to the out pin with respect to the ground 8. guaranteed by design and characterization, not production tested. timings figure 3. enable, rise and fall time v in en v out t en t r t on t off t dis t f
ncp432, ncp433 http://onsemi.com 5 typical characteristics 160 140 120 100 80 60 40 20 0 01 4 3 2 v in (v) i in ( a) temp = ? 40 c temp = 25 c temp = 85 c figure 4. standby current versus temperature 1.2 01 4 3 2 v in (v) i in ( a) 1.0 0.8 0.6 0.4 0.2 0 temp = ? 40 c temp = 25 c temp = 85 c figure 5. quiescent current versus temperature 300 01 4 3 2 v in (v) r ds(on) (m ) 250 200 150 100 50 0 figure 6. r ds(on) versus v in , 25 c, 100 ma load i load = 100 ma 350 01 4 3 2 v in (v) r ds(on) (m ) 300 250 200 150 100 50 0 ? 40 c 0 c 50 c ? 25 c 25 c 85 c i load = 100 ma figure 7. r ds(on) versus temperature, 100 ma load functional description overview the ncp432 ? ncp433 are high side p channel mosfet power distribution switch designed to isolate ics connected on the battery in order to save energy. the part can be turned on, with a range of battery from 1.0 v to 3.6 v. enable input enable pin is an active high. the path is opened when en pin is tied low (disable), forcing p mos switch off. the in/out path is activated with a minimum of vin of 1.0 v and en forced to high level. auto discharge (ncp433 only) nmos fet is placed between the output pin and gnd, in order to discharge the application capacitor connected on out pin. the auto ? discharge is activated when en pin is set to low level (disable state). the discharge path ( pull down nmos) stays activated as long as en pin is set at low level and v in > 1.0 v. in order to limit the current across the internal discharge n ? mosfet, the typical value is set at 65 . cin and cout capacitors in and out, 1 f, at least, capacitors must be placed as close as possible the part for stability improvement.
ncp432, ncp433 http://onsemi.com 6 application information power dissipation main contributor in term of junction temperature is the power dissipation of the power mosfet. assuming this, the power dissipation and the junction temperature in normal mode can be calculated with the following equations: p d r ds(on) i out 2 p d = power dissipation (w) r ds(on) = power mosfet on resistance ( ) i out = output current (a) t j p d r ja t a t j = junction temperature ( c) r ja = package thermal resistance ( c/w) t a = ambient temperature ( c) pcb recommendations the ncp432 ? ncp433 integrate an up to 1.5 a rated pmos fet, and the pcb design rules must be respected to properly evacuate the heat out of the silicon. by increasing pcb area, especially around in and out pins, the r ja of the package can be decreased, allowing higher power dissipation. ordering information device marking package shipping ? NCP432FCT2G av wlcsp4 (pb ? free) 3000 / tape & reel ncp433fct2g at wlcsp4 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp432, ncp433 http://onsemi.com 7 package dimensions case 567fj issue o seating plane 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max 0.57 millimeters a1 d 0.76 bsc e b 0.24 0.28 e 0.40 bsc 0.63 d e a b pin a1 reference e a 0.05 b c 0.03 c 0.05 c 4x b 12 b a 0.05 c a a1 a2 c 0.18 0.23 0.76 bsc 0.05 c 2x top view side view bottom view note 3 e a2 0.40 ref pitch 0.20 4x dimensions: millimeters *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.40 0.40 recommended a1 package outline pitch on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp432/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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